This invention relates to semiconductor switching devices, and more specifically relates to a novel structure and process of manufacture of a high speed switching device which employs two D-MOS type transistors which are merged together to have a common gate.
High power switching devices using MOS gate techniques are well known. One device, which is improved by the present invention, is the device known as a TRIMOS type device (an MOS controlled triac). The TRIMOS device consists generally of two D-MOS transistors which are merged together and employ a common drain and have insulated metal gates. The TRIMOS device is described in ELECTRONIC DESIGN 4, Feb. 15, 1978, pages 32 to 34, in an article entitled MOS-CONTROLLED TRIAC COMBINED LOW INPUT POWER, HIGH OUTPUT POWER. This same device is also described in U.S. Pat. No. 4,199,774, entitled MONOLITHIC SEMICONDUCTOR SWITCHING DEVICE, in the name of James D. Plummer.
In manufacturing the above device, it has been common to use self-aligned diffusion techniques for the formation of the two transistors. However, a relatively high conductivity region of the same type as the substrate is formed between the two conduction channels centered beneath their gate electrodes to prevent inversion of the otherwise relatively lightly doped material when the gate voltages are appropriate. The inversion of this intermediate layer would interfere with the correct operation of the TRIMOS device.
The formation of this N+ region required a separate diffusion and separate alignment step from the diffusion and alignment used in the manufacture of the transistor portions of the structure. Consequently, the device is very difficult to manufacture and is relatively expensive. Furthermore, the electric field surrounding the D-MOS transistors curves sharply within the device body, thus limiting the device to withstand more than a relatively low reverse voltage. For example, the devices have not been able to withstand more than about 200 volts.